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| For Information Equipment MN89303A SVGA Display Controller Overview The MN89303A is an LCD/CRT display controller with IBMTM VGA-compatible registers. It features all the necessary interfaces for a compact display system: ISA bus interface, local bus interface, DRAM interface, and LCD panel interface. The built-in graphics acceleration functions include support for hardware cursor. Note: IBMTM and VGA are registered trademarks of International Business Machines Corporation. Features Monochrome STN LCD panel support Maximum display size: 800 x 600 Support for single and dual panels 16-monochrome gradation Color STN LCD panel support Maximum display size: 800 x 600 Support for single and dual panels 16-gradation for each color (RGB) Color TFT LCD panel support Maximum display size: 800 x 600 4-bit output for each color (RGB) Maximum number of colors in concurrent display 640 x 480: 256/4096 palette (TFT, STN) 800 x 600: 256/4096 palette (TFT, STN) Built-in graphics acceleration functions * Hardware cursor (16 x 16 or 32 x 32) Built-in automatic display centering Built-in gradation control table (rewritable) for optimizing gradation to match panel DRAM interface with 16-bit bus * Choice of DRAM access timing to match system performance (EDO/normal) * Support for 2CAS/2WE mode * Refresh control Host interfaces * ISA bus (16-bit) * i386/i486 local bus (16-bit) Note: i386 and i486 are trademarks of Intel Corporation. Applications Point-of-sale terminals, Factory automation terminals, word processors, and other terminals 325 MN89303A Pin Assignment For Information Equipment 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 VDD VSS LOGICON LCDON BACKON LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 VDD VSS UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 MAO VSS VDD RAS UCAS LCAS WE MD15 MD14 MD13 MD12 MD11 MD10 VSS VDD MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 VSS VDD RESET MINTEST TEST VSS XOUT 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FP LP DISP DCLK VDD VSS IOCS16 MEMCS16 IOCHRDY VDD VSS SD0 SD1 SD2 SD3 SD4 SD5 VSS SD6 SD7 SD8 VDD SD9 SD10 SD11 VSS SD12 SD13 SD14 SD15 VDD VSS Note: Never leave VDD and VSS pins open. XIN VSS AEN SBHE IOWR IORD SMEMW SMEMR A21 A20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 BIOSEN REFRESH (TOP VIEW) QFH128-P-1818 For Information Equipment Block Diagram MN89303A Gray scale engine RAM table UD[7:0] LD[7:0] BACKON LCDON LOGICON LP FO DISP DCLK XIN RESET TEST/MINTEST 83 84 85 63 64 62 61 1 124 126/125 Hardware cursor LCD panel controller Attribute control LCD/CRT controller Video FIFO Address[21:0] SD[15:0] AEN SBHE IOWR IORD SMEMW SMEMR IOCHRDY REFRESH MEMCS16 IOCS16 3 4 5 6 7 8 56 32 57 58 Memory interface Access attributer Host interface Memory write buffer Graphics controller MA[9:0] MD[15:0] 100 RAS 101 UCAS 102 LCAS 103 WE 31 BIOSEN MN89303A Pin Descriptions Pin No. 3 Symbol AEN I/O I Level TTL Address Enable For Information Equipment Function Description "H" level input from this pin indicates that a DMA transfer is in progress, so the chip does not respond to I/O access. 4 5 6 7 SBHE IOWR IORD SMEMW I I I I TTL TTL TTL TTL Byte High Enable This input indicates the state of the 16-bit bus. I/O Write This input indicates an I/O write request. I/O Read This input indicates an I/O read request. Memory Write This input indicates a memory write request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 8 SMEMR I TTL Memory Read This input indicates a memory read request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 9 to 10 11 to 30 35 to 53 56 57 A[21:20] SA[19:0] SD[15:0] IOCHRDY MEMCS16 I I I/O I/O O TTL TTL TTL TTL TTL Address[21:20] These inputs give the address 21:20. Address[19:0] These inputs give the address 19:0. Data[15:0] These pins represent the host data bus. I/O Channel Ready This pin is "L" level when I/O or memory access is given wait state. Memory Chip Select 16 This output indicates to the system that 16-bit memory access is available. 58 32 88 to 97 100 101 IOCS16 REFRESH MA[9:0] RAS UCAS O I O O O TTL TTL CMOS CMOS CMOS I/O Chip Select 16 This output indicates to the system that 16-bit I/O access is available. Refresh "L" level input indicates that the system is refreshing its DRAM. Memory Address These outputs give the address of the display memory. Row Address Strobe (RAS) This output is the strobe signal for the row address latch. Upper Column Address Strobe (UCAS) This output is the strobe signal for the upper column address latch. In the 2WE mode, however, it functions as the CAS signal. For Information Equipment Pin Descriptions (continued) Pin No. 102 Symbol LCAS I/O O Level CMOS Function Description Lower Column Address Strobe (LCAS) MN89303A This output is the strobe signal for the lower column address latch. In the 2WE mode, however, it functions as the LWE signal. 103 WE O CMOS Write Enable This output is the data write signal. In the 2WE mode, however, it functions as the UWE signal. 104 to 121 MD[15:0] 31 83 BIOSEN BACKON I/O O O TTL CMOS CMOS Memory Data These pins represent the data bus to the DRAM. BIOS Enable This output enables ROM BIOS output. Backlight ON This output requests backlighting. "L" level: OFF; "H" level: ON 84 LCDON O CMOS LCD Drive ON This output requests power-ON for the LCD panel. "L" level: OFF; "H" level: ON 85 LOGICON O CMOS LCD Logic ON This output requests power-ON for LCD panel logic circuits. "L" level: OFF; "H" level: ON 63 LP O CMOS Line Pulse This output provides pulses indicating the end of a line of the LCD panel. 64 FP O CMOS Frame Pulse This output provides pulses indicating the start of a frame of the LCD panel. 62 DISP O CMOS Display Enable This output enables the LCD display. An external RAMDAC uses this signal as a blanking signal. A TFT LCD uses it as an enable signal. 61 DCLK O CMOS Data Shift Clock This pin provides a data shift clock signal for an STN LCD panel. It also outputs a dot clock signal on a TFT LCD panel or external RAMDAC display mode. 65 to 72 75 to 82 UD[7:0] LD[7:0] O O CMOS CMOS Upper Data[7:0] Lower Data[7:0] This pins provide display data. Usage varies with the LCD panel type. MN89303A Pin Descriptions (continued) Pin No. 124 Symbol RESET I/O I Level TTL Reset For Information Equipment Function Description "H" level input from this pin initializes the chip. If the host is in a i386 mode, the chip aligns the clock phase with this signal. 96 to 97 MA[1:0] I CMOS Host Type During a reset, these pins select the host type. MA[1:0] 0 0 1 1 0 1 0 1 Host Type ISA 386SX 386DX 486 126/125 1/128 TEST/ MINTEST XIN/ XOUT I/O CMOS Chip Test Condition This pin selects the chip test mode. Clock IN/OUT These pins are the clock I/O pins. Connect them to a crystal oscillator. Absolute Maximum Ratings Parameter Power supply voltage Input pin voltage Output pin voltage Power dissipaiton Operating ambient temperature Storage temperature Symbol VDD VI VO PD T opr Tstg Ratings - 0.3 to +7.0 - 0.3 to V DD+0.3 - 0.3 to V DD+0.3 1000 0 to +70 - 55 to +150 Unit V V V mW C C Recommended Operating Conditions Parameter Power supply voltage Ambient temperature Rise time for input Fall time for input Oscillation frequency Operating frequency Operating frequency Symbol VDD Ta tr tf f OSC fopr1 fopr2 At self-excited operation At self-excited operation Using external input Conditions min 4.75 0 0 0 25 25 0 typ 5.00 max 5.25 70 150 150 33 33 33 Unit V C ns ns MHz MHz MHz For Information Equipment Electrical Characteristics VDD =4.75 to 5.25V, VSS=0.00V, f=33MHz, Ta=0 to 70C Parameter Power supply current during operation Power supply current in the SUSPEND mode Power supply current in the STANDBY mode "H" level input voltage 1 TEST ,AEN ,SBHE , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "H" level input voltage 2 MINTEST ,RAS ,UCAS , LCAS ,BACKON , LCDON ,LOGICON , MA9 to 0 "L" level input voltage 1 TEST ,AEN ,SBHE , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "L" level input voltage 2 MINTESTRAS UCAS , LCAS ,BACKON , LCDON ,LOGICON , MA9 to 0 Input leakage current 1 TEST ,MINTEST Input leakage current 2 AEN ,SBHE ,IOWR , IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , RESET Pull-down resistance Input threshold voltage RESET RPD1 VtHL VtLH VI=VDD ,VDD =5.0V VDD=4.75 to 5.25V 12 30 1.0 1.8 ILI2 VI=VDD or VSS ILI1 VI=VDD or VSS VIL2 0 VIL1 0 VIH2 VDD x 0.7 VIH1 2.0 IDD2 VI=VDD or VSS ,V DD=5.0V IDD1 VI=VDD or VSS ,V DD=5.0V Symbol IDD0 Conditions VI=VDD or VSS ,V DD=5.0V min typ MN89303A max 120 15 40 VDD Unit mA mA mA V VDD V 0.8 V VDD x 0.3 V 20 10 A A 75 k V MN89303A Electrical Characteristics (continued) VDD =4.75 to 5.25V, VSS =0.00V, f=33MHz, Ta=0 to 70C Parameter "H" level output voltage 1 BACKON ,LCDON , LOGICON ,SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 , WE ,MA9 to 0 ,RAS , UCAS ,LCAS "H" level output voltage 3 IOCHRDY "H" level output voltage 4 IOCS16 ,MEMCS16 "L" level output voltage 1 BACKON ,LCDON , LOGICON "L" level output voltage 2 SD15 to 0 ,MD15 to 0 , BIOSEN "L" level output voltage 3 DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 , WE ,MA9 to 0 ,RAS , UCAS ,LCAS "L" level output voltage 4 IOCHRDY "L" level output voltage 5 IOCS16 ,MEMCS16 Output leakage current IOCS16 ,BACKON , MA9 to 0 ,MEMCS16 , UCAS ,LCAS ,RAS , LOGICON ,LCDON , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY ILO V OL5 V OL4 IO=12.0mA VI=V DD or VSS IO=16.0mA VI=V DD or VSS VO=High-impedance state VI=V DD or VSS VO=VDD or VSS V OL3 IO=0.8mA VI=V DD or VSS V OL2 IO=4.0mA VI=V DD or VSS V OL1 VOH4 VOH3 IO=-12.0mA VI=V DD or VSS IO=-16.0mA VI=V DD or VSS IO=2.0mA VI=V DD or VSS VOH2 IO=-8.0mA VI=V DD or VSS Symbol VOH1 Conditions IO=-2.0mA VI=V DD or VSS For Information Equipment min VDD- 0.6 typ max Unit V VDD- 0.6 V VDD- 0.6 VDD- 0.6 0.4 V V V 0.4 V 0.4 V 0.4 0.4 10 V V A For Information Equipment Timing Chart for LCD Panel Outputs MN89303A FP LP DCLK LD7/UD7 LD6/UD6 LD5/UD5 LD4/UD4 LD3/UD3 LD2/UD2 LD1/UD1 LD0/UD0 FP LP UD LD 240 lines 480 lines 1 line 241 lines 2 lines 242 lines 3 lines 243 lines 4 lines 244 lines 5 lines 245 lines R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G638 B638 R639 G639 B639 R640 G640 B640 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 1 2 3 640 R640 G640 B640 UD2 UD1 UD0 1 line 2 lines R1 G1 B1 R2 G2 B2 R3 G3 B3 UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 UD7 First byte of data Upper screen * * * * * 240 lines 241 lines 242 lines R1 G1 B1 R2 G2 B2 R3 G3 B3 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LD7 First byte of data Lower screen R640 G640 B640 LD2 LD1 LD0 * * * * * * * 480 lines MN89303A Application Circuit Example For Information Equipment BIOS CE (20) RESET Address[21:0] SD[15:0] BIOSEN XOUT XIN UD[7:0] LD[7:0] AEN SBHE IOWR IORD SMEMW SMEMR REFRESH IOCHRDY DISP BACKON LCDON LCD MN89303A LOGICON panel LP FP MD[15:0] MEMCS16 BIOSEN MA[9:0] 4MDRAM ISA bus RAS IOCS16 UCAS LCAS DCLK WE For Information Equipment Package Dimensions (Unit: mm) QFH128-P-1818 MN89303A 20.00.2 18.00.2 96 97 65 64 (1.25) 33 1 0.5 32 0.20.1 18.00.2 20.00.2 128 (1.25) 1.00.2 3.30.2 3.40.3 0.15-0.05 +0.10 0.10.1 0.1 SEATING PLANE 0.50.2 0 to 10 |
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